3.1.3
Register Configuration
The MMU registers are shown in table 3.1.
Table 3.1 MMU Registers
Abbrevia-
tion
Initial
R/W Value
P4
Address
Area 7
Address
Access
Size
1
*
2
*
2
*
Name
Page table entry high
register
PTEH
R/W Undefined
R/W Undefined
R/W Undefined
R/W Undefined
R/W Undefined
H'FF00 0000 H'1F00 0000 32
H'FF00 0004 H'1F00 0004 32
H'FF00 0034 H'1F00 0034 32
H'FF00 0008 H'1F00 0008 32
H'FF00 000C H'1F00 000C 32
Page table entry low
register
PTEL
PTEA
TTB
Page table entry
assistance register
Translation table base
register
TLB exception address TEA
register
MMU control register
MMUCR
R/W H'0000 0000 H'FF00 0010 H'1F00 0010 32
Notes: *1 The initial value is the value after a power-on reset or manual reset.
*2 This is the address when using the virtual/physical address space P4 area. When
making an access from physical address space area 7 using the TLB, the upper 3 bits
of the address are ignored.
3.1.4
Caution
Operation is not guaranteed if an area designated as a reserved area in this manual is accessed.
Rev. 6.0, 07/02, page 60 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
