From any state when
= 0 and
From any state when
= 0 and
= 1
= 0
Power-on reset state
Manual reset state
= 0,
= 1
Reset state
= 1,
= 1
= 1,
= 0
Exception-handling state
Bus request
Bus request
clearance
Interrupt
Interrupt
Exception
interrupt
End of exception
transition
Bus-released state
processing
Bus request
clearance
Bus
request
Bus request
clearance
Bus request
Program execution state
SLEEP instruction
with STBY bit
cleared
SLEEP instruction
with STBY bit set
Sleep mode
Standby mode
Power-down state
Figure 2.6 Processor State Transitions
2.7
Processor Modes
There are two processor modes: user mode and privileged mode. The processor mode is
determined by the processor mode bit (MD) in the status register (SR). User mode is selected
when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset
state or exception state is entered, the MD bit is set to 1. There are certain registers and bits which
can only be accessed in privileged mode.
Rev. 6.0, 07/02, page 55 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
