Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001)
31
22 21 20 19 18 17
FR SZ PR DN
12 11
7
6
2
1
0
—
Cause
Enable
Flag
RM
Note: —: Reserved. These bits are always read as 0, and should only be written with 0.
•
FR: Floating-point register bank
FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1–
FPR15_BANK1 are assigned to XF0–XF15.
FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1–
FPR15_BANK1 are assigned to FR0–FR15.
•
•
SZ: Transfer size mode
SZ = 0: The data size of the FMOV instruction is 32 bits.
SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).
PR: Precision mode
PR = 0: Floating-point instructions are executed as single-precision operations.
PR = 1: Floating-point instructions are executed as double-precision operations (the result of
instructions for which double-precision is not supported is undefined).
Do not set SZ and PR to 1 simultaneously; this setting is reserved.
[SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)
•
DN: Denormalization mode
DN = 0: A denormalized number is treated as such.
DN = 1: A denormalized number is treated as zero.
•
•
•
Cause: FPU exception cause field
Enable: FPU exception enable field
Flag: FPU exception flag field
FPU
Invalid
Division
Overflow Underflow Inexact
Error (E) Operation (V) by Zero (Z) (O)
(U)
(I)
Cause
FPU exception Bit 17
cause field
Bit 16
Bit 11
Bit 6
Bit 15
Bit 10
Bit 5
Bit 14
Bit 9
Bit 4
Bit 13
Bit 12
Enable FPU exception None
enable field
Bit 8
Bit 3
Bit 7
Bit 2
Flag
FPU exception None
flag field
Rev. 6.0, 07/02, page 51 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
