Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and
FPR0_BANK1–FPR15_BANK1 are undefined.
2.2.4
Control Registers
Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000
00XX 1111 00XX (X: undefined))
31 30 29 28 27
MD RB BL
16 15 14
FD
10
9
8
7
4
3
2
1
0
T
—
—
—
M
Q
IMASK
—
S
Note: —: Reserved. These bits are always read as 0, and should only be written with 0.
•
•
MD: Processor mode
MD = 0: User mode (some instructions cannot be executed, and some resources cannot be
accessed)
MD = 1: Privileged mode
RB: General register bank specifier in privileged mode (set to 1 by a reset, exception, or
interrupt)
RB = 0: R0_BANK0–R7_BANK0 are accessed as general registers R0–R7. (R0_BANK1–
R7_BANK1 can be accessed using LDC/STC R0_BANK–R7_BANK instructions.)
RB = 1: R0_BANK1–R7_BANK1 are accessed as general registers R0–R7. (R0_BANK0–
R7_BANK0 can be accessed using LDC/STC R0_BANK–R7_BANK instructions.)
•
•
BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt)
BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs
while BL = 1, the processor switches to the reset state.
FD: FPU disable bit (cleared to 0 by a reset)
FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction
is in a delay slot, a slot FPU disable exception is generated. (FPU instructions: H'F***
instructions, LDC(.L)/STS(.L) instructions for FPUL/FPSCR)
•
•
M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions.
IMASK: Interrupt mask level
External interrupts of a same level or a lower level than IMASK are masked.
•
•
S: Specifies a saturation operation for a MAC instruction.
T: True/false condition or carry/borrow bit
Rev. 6.0, 07/02, page 49 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
