7906 参数 Datasheet PDF下载

CLOCK GENERATING CIRCUIT

[Precautions for clock generating circuit]

[Precautions for clock generating circuit]

1. While pin RESET = “L” level and after reset, the PLL frequency multiplier is inactive. Clear the PLL circuit

operation enable bit (bit 1 at address BC

16

) to “0” if the PLL frequency multiplier needs not to be active.

2. To select f

PLL

as f

sys

after reset, set the system clock select bit (bit 5 at address BC

16

) to “1” 2 ms after

f(X

IN

) has been stabilized. (See Figure 4.2.3.)

3. To change the multiplication ratio for the PLL frequency multiplier, clear the system clock select bit (bit

5 at address BC

16

) to “0” simultaneously. Then, set the system clock select bit to “1” 2 ms after the

rewriting of the PLL multiplication ratio select bits (bits 2, 3 at address BC

16

). (See Figure 4.2.3.)

After reset, the PLL multiplication ratio select bits are allowed to be changed only once. If it is necessary

to write a certain value to these bits, be sure to write the same value that has been written after the latest

reset.

7906 Group User’s Manual Rev.2.0

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