RESET
3.4 Internal processing sequence after reset
3.4 Internal processing sequence after reset
Figure 3.4.1 shows the internal processing sequence after reset.
f
sys
�½
A
H(CPU)
�½
�½
00
16
0000
16
Undefined
IPL, Vector addresses of reset
00
16
FFFE
16
AD
15
to AD
0
00
16
AD
15
to AD
0
Next op-code
A
L
A
M(CPU)
DATA
(CPU)
�½
f
sys
: System clock (See Figure 4.2.1.)
AD
0
to AD
15
: Internal address bus
IPL : Processor interrupt priority level
�½
This is an internal signal and is not output to the external.
Fig. 3.4.1 Internal processing sequence after reset
7906 Group User’s Manual Rev.2.0
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