RESET
3.4 Internal processing sequence after reset
3.4 Internal processing sequence after reset
Figure 3.4.1 shows the internal processing sequence after reset.
➀
f
sys
➀
0016
0016
0016
A
A
H(CPU)
➀
A
L
M(CPU)
AD15 to AD
0
000016
FFFE16
➀
IPL, Vector addresses of reset
Next op-code
Undefined
AD15 to AD
0
DATA(CPU)
f
sys : System clock (See Figure 4.2.1.)
AD0
to AD 15 : Internal address bus
IPL : Processor interrupt priority level
➀ This is an internal signal and is not output to the external.
Fig. 3.4.1 Internal processing sequence after reset
7906 Group User’s Manual Rev.2.0
3-15
RENESAS [ RENESAS TECHNOLOGY CORP ]
