CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
Address
Address
(Note 5)
(Note 5)
(Note 5)
A016
A116
A216
A316
A416
A516
A616
A716
A816
A916
AA16
AB16
AC16
AD16
AE16
AF16
B016
B116
B216
B316
B416
B516
B616
B716
B816
B916
BA16
BB16
BC16
BD16
BE16
BF16
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
Up-down flag 1
Waveform output mode register
Dead-time timer
Timer A5 register
Timer A6 register
Timer A7 register
Timer A8 register
Timer A9 register
Three-phase output data register 0
Three-phase output data register 1
Position-data-retain function control register
Serial I/O pin control register
Port P2 pin function control register
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
Timer A0
Timer A1
Timer A2
1
1
1
register
register
register
Timer A5 mode register
Timer A6 mode register
Timer A7 mode register
Timer A8 mode register
Timer A9 mode register
(Note 5)
(Note 5)
(Note 5)
Comparator function select register 0
Clock control register 0
(Note 5)
(Note 5)
Comparator result register 0
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
Timer A5 interrupt control register
Timer A6 interrupt control register
Timer A7 interrupt control register
Timer A8 interrupt control register
Timer A9 interrupt control register
INT
INT
INT
5
6
7
interrupt control register
interrupt control register
interrupt control register
Note 5: Do not write to this register.
Fig. 2.4.3 SFR area’s memory map (2)
7906 Group User’s Manual Rev.2.0
2-18
RENESAS [ RENESAS TECHNOLOGY CORP ]
