CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
0
16
→ See Figures 2.4.2
SFR area
Interrupt vector table
Reserved area
Reserved area
Timer A9
FF16
and 2.4.3.
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
FFB416
FFB616
FFB816
FFBA16
FFBC16
Timer A8
Timer A7
Timer A6
Timer A5
Internal RAM area
FFBE16
FFC016
FFC216
FFC416
FFC616
FFC816
INT
INT
INT
7
6
5
Reserved area
Address matching detection
Reserved area
Reserved area
FFCA16
FFCC16
FFCE16
FFD016
FFD216
FFD416
INT
4
3
INT
A-D conversion
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
FFD616
FFD816
FFDA16
FFDC16
FFDE16
FFE016
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Internal ROM area
Timer B1
FFE216
FFE416
FFE616
FFE816
FFEA16
FFEC16
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
FFEE16
FFF016
FFF216
FFF416
FFF616
Reserved area
Reserved area
Reserved area
Reserved area
Watchdog timer
FFB416
FFFF16
H
L
H
L
H
L
H
L
FFF816
FFFA16
FFFC16
FFFE16
DBC (Note 1)
BRK instruction (Note 1)
Zero divide
RESET
H
L
H
: The internal memory is not assigned.
Notes 1: These are interrupts only for debugging; do not use these interrupts.
2: Memory assignment of the internal area varies according to the product type. Refer to section
“Appendix 11. Memory assignment of 7906 Group” or the latest datasheets, catalogues.
Fig. 2.4.1 Memory assignment in internal area
7906 Group User’s Manual Rev.2.0
2-16
RENESAS [ RENESAS TECHNOLOGY CORP ]
