FLASH MEMORY VERSION
19.2 Flash memory CPU reprogramming mode
19.2.2 Status register
The programming and erase operations for the internal flash memory are controlled by the sequencer in
the internal flash memory. The status register indicates the completion states (normal or abnormal) of the
programming and erase operations. For details of abnormal endings (errors), refer to section “19.2.5 Full
status check.”
Table 19.2.2 lists the bit definition of the status register.
The contents of the status register can be read out by the read status register command. (Refer to section
“19.2.4 Software commands.”)
Table 19.2.2 Bit definition of status register
Definition
Symbol
(Data bus)
Status
“1”
“0”
SR.0 (D0)
SR.1 (D1)
SR.2 (D2)
SR.3 (D3)
SR.4 (D4)
SR.5 (D5)
SR.6 (D6)
SR.7 (D7)
—
—
—
—
—
—
—
—
—
—
—
—
Programming Status
Terminated normally.
Error<Programming error>
Erase Status
Terminated normally.
Error<Erase error>
—
—
—
—
—
—
Data bus: Indicates the data bus to be read out when the read status register command has been executed.
(1) Programming status bit (SR.4)
This bit is set to “1” if a programming error has occurred during the automatic programming (the
programming) operation and cleared to “0” by executing the clear status register command. This bit
is also cleared to “0” at reset.
(2) Erase status bit (SR.5)
This bit is set to “1” if an erase error has occurred during the automatic erase (the block erase or
erase all unlocked blocks) operation and cleared to “0” by executing the clear status register command.
This bit is also cleared to “0” at reset.
7906 Group User’s Manual Rev.2.0
19-12
RENESAS [ RENESAS TECHNOLOGY CORP ]
