FLASH MEMORY VERSION
19.2 Flash memory CPU reprogramming mode
19.2.5. Full status check
If an error has occurred, bits SR.4 and SR.5 of the status register are set to “1” upon completion of the
programming or erase operation. Therefore, the result of the programming or erase operation can be
recognized by checking these status (in other words, full status check).
Table 19.2.3 lists the errors and the states of bits SR.4 and SR.5, and Figure 19.2.6 shows the full status
check flowchart and the action to be taken if any error has occurred.
Table 19.2.3 Errors and States of bits SR.3 to SR.5
Status register
Error
Error occurrence conditions
SR.4
1
SR.5
1
Command sequen-
ce error
• Commands are not correctly written.
• Data other than “D016” and “FF16” is written at the 2nd bus cycle of the
block erase command (Note).
• Data other than“2016” and “FF16” is written at the 2nd bus cycle of the
erase-all-blocks command (Note).
Erase error
• Although the block erase or erase-all-blocks command is executed,
these blocks are not correctly erased.
0
1
1
0
Programming error • Although the programming command is executed, programming is not
correctly performed.
Notes: When “FF16” is written at the 2nd bus cycle of any of these commands, the microcomputer enters the read
array mode. Simultaneously with this, the command code written at the 1st bus cycle is cancelled.
Read status register
SR.4 = 1
Command sequence
• • • •
and
✕ Execute the clear status command to clear SR.4 and SR.5 to “0.”
✕ Execute the correct command again.
Note: If the same error occurs, however, the block cannot be used.
error
YES
SR.5 = 1
?
NO
SR.5 = 0?
YES
✕✕Execute the clear status command to clear SR.5 to “0.”
✕ Execute the block erase or erase-all-unlocked-blocks command again.
Note: If the same error occurs, however, the block cannot be used.
Erase error
• • • •
NO
NO
• • • • ✕ Execute the clear status command to clear SR.4 to “0.”
✕ Execute the programming command again.
SR.4 = 0?
YES
Programming error
Note: If the same error occurs, however, the block cannot be used.
Completed.
Note: Under the condition that any of SR.4 and SR.5 = “1,” none of the programming, block erase, erase-all-blocks commands can be
accepted. To execute any of these commands, in advance, execute the clear status register command.
Fig. 19.2.6 Full status check flowchart and actions to be taken if any error has ocurred
7906 Group User’s Manual Rev.2.0
19-16
RENESAS [ RENESAS TECHNOLOGY CORP ]
