FLASH MEMORY VERSION
19.2 Flash memory CPU reprogramming mode
19.2.3 Setting and Terminate procedure for flash memory CPU reprogramming mode
Figure 19.2.2 shows the setting and terminate procedures for the flash memory CPU reprogramming mode.
In the flash memory CPU reprogramming mode, opcodes cannot be fetched for the internal flash memory.
Therefore, be sure to transfer the reprogramming control software to an area other than the internal flash
memory and then execute the software in that area.
Moreover, in order to prevent any interrupt occurrence during the flash memory CPU reprogramming mode,
before selecting this mode, be sure to set the interrupt disable flag (I) to “1” or set the interrupt priority level
to “000 ” (interrupts disabled).
2
Also, we recommend to connect pin P6OUTCUT with VCC via a resistor.
Even in the flash memory CPU reprogramming mode, periodically writing to the watchdog timer is required
in order to prevent the watchdog timer interrupt occurrence.
At the same time, it is necessary to write to the watchdog timer just before executing the programming,
block erase, or erase all blocks command in order to prevent the watchdog timer interrupt occurrence
during the automatic programming and erase operation.
An interrupt, hardware reset, or software reset, generated in the flash memory CPU reprogramming mode,
makes program runaway. If a program runaway has occurred, be sure to push the microcomputer into the
power-on reset state.
When an interrupt or reset is generated during the programming or erase operation, the contents of the
corresponding block becomes invalidated.
Reprogramming control
software
Single-chip mode,
or Boot mode
User ROM area select bit ← “1”
(Only in the boot mode)
Internal ROM bus cycle select bit ← “0”
CPU reprogramming mode select bit ← “0”
(bit 7 at address 5F16
)
CPU reprogramming mode select bit ← “1”
Interrupt disable flag (I) = “1”
or Interrupt priority level of each interrupt = “0002”
Software command is executed.
Read array command is executed,
or Flash memory reset bit ← “1”
Flash memory reset bit ← “0”
(Notes 1, 2)
The reprogramming control software for the flash
memory CPU reprogramming mode is transferred
to an area other than the internal flash memory.
Jump to the control software transferred in the
above procedure
(The subsequent procedures will be executed
CPU reprogramming mode select bit ← “0”
.
by the reprogramming control software trans-
ferred in the above procedure.)
User ROM area select bit ← “0”
(Only in the boot mode ) (Note 3)
Jump to an arbitrary address in the
internal flash memory area.
Notes 1: Before termination of the flash memory CPU reprogramming mode, be sure to execute the read array
.
command or flash memory reset
2: After writing of “1” to the flash memory reset bit, be sure to confirm the RY/BY status bit (bit 0 at address
9E16) becomes “1”; and then, write “0” to this bit.
3: When the flash memory CPU reprogramming mode has been terminated with the user ROM area select
bit (bit 5 at address 9E16) = “1,” the access to the user ROM area is selected.
Fig. 19.2.2 Setting and Terminate procedures for flash memory CPU reprogramming mode
7906 Group User’s Manual Rev.2.0
19-13
RENESAS [ RENESAS TECHNOLOGY CORP ]
