FLASH MEMORY VERSION
19.1 Overview
19.1.2 Single-chip mode
When being reset with both of pins MD1 and MD0 tied to Vss level, the microcomputer enters the single-
chip mode. In the single-chip mode, the software in the user ROM area is executed after reset.
The difference between the flash memory version and the mask ROM version is as follows:
ꢀꢀStop mode terminate operation
(1) Stop mode terminate operation
Figure 19.1.3 shows stop mode terminate sequence owing to an interrupt request occurrence in the
flash memory version. (Refer from section “Stop mode”.)
In the flash memory version, when the watchdog timer is not used for termination of the stop mode,
an interrupt request is accepted after a maximum of 10 µs has elapsed since the interrupt request
occurred.
7906 Group User’s Manual Rev.2.0
19-6
RENESAS [ RENESAS TECHNOLOGY CORP ]
