FLASH MEMORY VERSION
19.1 Overview
ꢀ When using the watchdog timer
Stop mode
fXIN
f
PLL (Note)
φ1
φBIU
Interrupt request to be
used for stop mode
termination
fXi
ꢀꢀ2048 counts
(Interrupt request bit)
FFF16
Value of watchdog timer
7FF16
CPU
Operating
Operating
Operate
Operate
Stopped
Stopped
Stopped
Operating
Internal peripheral device
ꢀꢀSTP
instruction
is executed.ꢀꢀOscillation stars.
(When an external clock is input
ꢀꢀInterrupt request to be used for
termination occurs.
ꢀꢀWatchdog timer's MSB = “0”
(However, watchdog timer interrupt
request dose not occur.)
ꢀ Each supplyꢀofꢀφCPU, φBIU starts.
from pin XIN, clock input starts.)
ꢀꢀPLL frequency multiplier starts its
operation.
ꢀ Interrupt request which was used for
termination is accepted.
ꢀ Watchdog timer starts counting.
Note: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.”
fXi
: fX16, fX32, fX64, fX128
There are clocks selected by the watchdog timer clock source bits at STP termination (bits 6, 7 at address 6116
)
ꢀ When not using the watchdog timer
Stop mode
fXIN
φ1
φBIU
Interrupt request to be
used for stop mode
termination
10µs (Max.)
FFF16
(Interrupt request bit)
Value of the watchdog timer
7FF16
CPU
Operating
Operating
Stopped
Stopped
Stopped
Operating
Operating
Operating
Internal peripheral device
ꢀꢀSTP
instruction
is executed.
ꢀꢀInterrupt request
to be used for
termination occurs.
ꢀꢀEach supplyꢀof φCPU, φBIU starts.
ꢀꢀInterrupt request which was used
for termination is accepted.
ꢀꢀClock input from pin XIN starts.
ꢀꢀWatchdog timer starts counting.
Fig. 19.1.3 Stop mode terminate sequence owing to interrupt request occurrence
7906 Group User’s Manual Rev.2.0
19-7
RENESAS [ RENESAS TECHNOLOGY CORP ]
