DEBUG FUNCTION
17.3 Address matching detection mode
17.3 Address matching detection mode
When the contents of PG and PC match with the specified address, an address matching detection interrupt
request occurs.
17.3.1 Setting procedure for address matching detection mode
Figure 17.3.1 shows an initial setting example for registers relevant to the address matching detection
mode.
Disables interrupts.
The interrupt disable flag (I) is set to “1.”
Selection of detect condition
b7
b0
b7
b0
Debug control register 1 (Address 6716
)
0
0
0
0
0
Debug control register 0 (Address 6616)
Address compare register access enable bit
(Note 1)
0 : Disabled.
Detect condition select bits
b2 b1 b0
0 0 1 : Address matching detection 0
0 1 0 : Address matching detection 1
0 1 1 : Address matching detection 2
Set the detect enable bit to “1.”
Detect enable bit
0 : Detection disabled.
b7
b0
Debug control register 0 (Address 6616
)
1
Detect enable bit
Processing for setting of address compare registers
1 : Detection enabled.
b7
b0
Debug control register 1 (Address 6716
)
1
1
0
Clear the interrupt disable flag (I) to “0” (Note 2).
Address compare register access enable bit
(Note 1)
1 : Enabled.
Setting of address compare registers
Detection starts.
b23
b0
Address compare register 0
(Addresses 6A16 to 6816
Address compare register 1
(Addresses 6D16 to 6B16
The address to be detected is set here.
)
Notes 1: Be sure to set this bit to “1” immediately before reading from or
writing to the address compare registers 0, 1. Then, be sure to
clear this bit to “0” immediately after this reading or writing.
2: This processing is unnecessary when no maskable interrupt is
used.
)
Fig. 17.3.1 Initial setting example for registers relevant to address matching detection mode
7906 Group User’s Manual Rev.2.0
17-6
RENESAS [ RENESAS TECHNOLOGY CORP ]
