DEBUG FUNCTION
17.2 Block description
17.2.3 Address compare registers 0 and 1
Each of the address compare registers 0 and 1 consists of 24 bits, and the address to be detected is set
here.
Figure 17.2.4 shows the structures of the address compare registers 0 and 1.
(b23) (b16)(b15) (b8)
b7
b0 b7
b0 b7
b0
Address compare register 0 (Addresses 6A16 to 6816)
Address compare register 1 (Addresses 6D16 to 6B16)
Bit
Function
At reset R/W
23 to 0 The address to be detected (in other words, the start address of instructions) is set here. Undefined RW
Note: When accessing to these registers, be sure to set the address compare register access enable bit (bit 2 at address 6716) to “1”
immediately before the access. Then, be sure to clear this bit to “0” immediately after this access.
Fig. 17.2.4 Structures of address compare registers 0 and 1
At op-code fetch, the contents of PG and PC are compared with the addresses being set in the address
compare register 0 or 1. Therefore, be sure to set the start address of an instruction into the address
compare register 0 or 1. If such an address as in the middle of instructions or in the data table is set into
the address compare register 0 or 1, no address matching detection interrupt request occurs because this
address does not match with the contents of PG and PC.
Note that, before the instruction at the address being set in the address compare register 0 or 1 is
executed, an address matching detection interrupt request occurs and is accepted.
7906 Group User’s Manual Rev.2.0
17-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
