STOP AND WAIT MODES
15.1 Overview
15.1 Overview
When there is no need for operation of the central processing unit (CPU), the stop and wait modes are used
to stop oscillation or internal clock. As a result, the power consumption can be saved. The microcomputer
enters the stop mode when the STP instruction has been executed; the microcomputer enters the wait mode
when the WIT instruction has been executed.
The stop and wait modes are terminated by an interrupt request occurrence or hardware reset.
Table 15.1.1 lists the states in the stop and wait modes and operations after these modes are terminated.
Table 15.1.1 States in stop and wait modes and operations after these modes are terminated
Wait mode
Stop mode
System clock is inactive.
(Bit 3 at address 6316 = “1”)
System clock is active.
When watchdog timer is used at When watchdog timer is not used
Item
termination (See Figure 15.3.1.) at termination (See Figure 15.3.1.) (Bit 3 at address 6316 = “0”)
Active.
Inactive.
Stopped.
Inactive.
Inactive.
Oscillation
PLL frequency multiplier
φCPU, φBIU
Operates (Note 1).
Inactive.
Active.
Inactive.
f
sys, clock
f1 to f4096
Wf32, Wf512
φ1,
Inactive.
Inactive.
Can operate only in the
event counter mode.
Can operate only when an
external clock is selected.
Stopped.
Operates.
Timers A, B
Can operate only in the event counter mode.
Operates.
Serial I/O
Can operate only when an external clock is
selected.
Stopped.
Operates.
Operates.
Stopped.
A-Dconverter
D-Aconverter
Watchdog timer
Pins
Stopped.
Stopped.
Stopped.
Retains the state at the STP instruction execution.
Retains the state at the WIT instruction execution.
Supply of φCPU, φBIU starts immediately after
termination.
Termination due
to interrupt request
occurrence
Supply of φCPU, φBIU starts after a
certain time has been measured
by using the watchdog timer.
Supply of φCPU, φBIU starts
immediately after termi-
nation (Note 2).
Termination due
Operation after hardware reset
Operation after hardware reset
to hardware reset
Notes 1: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.”
2: See Table 15.3.2.
7906 Group User’s Manual Rev.2.0
15-2
RENESAS [ RENESAS TECHNOLOGY CORP ]
