SERIAL I/O
11.2 Block description
11.2.1 UARTi transmit/receive mode register
Figure 11.2.2 shows the structure of UARTi transmit/receive mode register.
b7 b6 b5 b4 b3 b2 b1 b0
At reset R/W
UART0 transmit/receive mode register (Address 3016
UART1 transmit/receive mode register (Address 3816
)
)
Function
Bit
0
Bit name
b2 b1b0
0
0
0
RW
RW
RW
Serial I/O mode select bits
0 0 0 : Serial I/O is invalid.
(P1 functions as a programmable I/O port.)
0 0 1 : Clock synchronous serial I/O mode
0 1 0 :
1
2
Do not select.
0 1 1 :
1 0 0 : UART mode (Transfer data length = 7 bits)
1 0 1 : UART mode (Transfer data length = 8 bits)
1 1 0 : UART mode (Transfer data length = 9 bits)
1 1 1 : Do not select.
Internal/External clock select bit
Stop bit length select bit
0 : Internal clock
1 : External clock
3
4
5
0
0
0
RW
RW
RW
0 : One stop bit
1 : Two stop bits
(Valid in UART mode)
(Note)
Odd/Even parity select bit
(Valid in UART mode when parity
0 : Odd parity
1 : Even parity
enable bit = “1.”)
(Note)
Parity enable bit
(Valid in UART mode)
0 : Parity disabled
1 : Parity enabled
6
7
0
0
RW
RW
(Note)
Sleep select bit
(Valid in UART mode)
0 : Sleep mode terminated (Invalid)
1 : Sleep mode selected
(Note)
Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.”
Fig. 11.2.2 Structure of UARTi transmit/receive mode register
7906 Group User’s Manual Rev.2.0
11-4
RENESAS [ RENESAS TECHNOLOGY CORP ]
