PULSE OUTPUT PORT MODE
9.3 Setting of pulse output port mode
From preceding “Figure 9.3.1”
Processing of avoiding undefined output before starting pulse output (Note)
b7
b0
Three-phase output data register 0 (Address A816
)
0
0
RTP00
RTP01
RTP02
Initial output data is set.
RTP03
RTP10
RTP11
Pulse output trigger select bits
Underflow of Timer A0
b7
b0
Three-phase output data register 1 (Address A916
)
➀ ➀ ➀ ➀
Pulse width modulation enable bit 0
Pulse width modulation enable bit 1
See Table 9.2.3.
Pulse width modulation enable bit 2
Pulse output polarity select bit
0 : Positive
1 : Negative
X : It may be either “0” or “1.”
b7
b0
Timer A0 mode register (Address 5616
)
0
0
0
0
0
0
0
0
Selection of count source f
2
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716 and 4616
)
0016
0016
A value of “000016” is set.
b7
b7
b0
Timer A0 interrupt control register (Address 7516
)
0
0
0
0
Interrupt disabled
No interrupt request
b0
Count start register 0 (Address 4016
)
Timer A0 count start bit
1 : Start counting
When an underflow occurs in timer A0, the contents of three-phase output data register 0 are output from the filp-flop.
(Pulse output pins are floating until the pulse output becomes enabled.)
b7
b0
Count start register 0 (Address 4016
)
Timer A0 count start bit
0 : Stop counting
This processing can be omitted when the system is not
affected by the undefined output.
Continue to “Figure 9.3.3.”
Fig. 9.3.2 Initial setting example for registers relevant to pulse output port mode (in pulse mode 1) (2)
7906 Group User’s Manual Rev.2.0
9-15
RENESAS [ RENESAS TECHNOLOGY CORP ]
