RESET
3.3 State of internal area
Address
Register name
Access characteristics
RW
State immediately after reset
b7
b0
b7
b0
0016
?
0016
Pulse output control register
A016
A116
A216
A316
A416
A516
A616
A716
A816
A916
AA16
AB16
AC16
AD16
AE16
AF16
B016
B116
B216
B316
B416
B516
B616
B716
B816
B916
BA16
BB16
BC16
BD16
BE16
BF16
Pulse output data register 0
Pulse output data register 1
RW
RW
?
0016
?
Waveform output mode register
Dead-time timer
RW
WO
RW
RW
0016
?
0016
Three-phase output data register 0
Three-phase output data register 1
Position-data-retain function control register
0016
0
?
0
0
0
0
0
0
0
RW RO RO RO
RW RW RW RW
RW RW RW
?
Serial I/O pin control register
0
0
0
0
0
0
0
0
RW RW
?
Port P2 pin function control register
RW
?
?
?
?
?
RW
WO
WO
UART2 transmit/receive mode register
UART2 baud rate register (BRG2)
0016
?
?
?
UART2 transmit buffer register
WO
RW
RO
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
RW
RO
RO
RW
RO
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
RW
0
?
RO
UART2 receive buffer register
0
0
0
0
0
0
?
0
(Note 16)
?
?
?
?
(Note 16)
(Note 16)
Clock control register 0
1
1
1
1
0
0
0
0
RW RW RW RW(Note 17)RW RW
(Note 16)
?
?
?
(Note 16)
(Note 16)
Notes 16 : Do not write to this register.
17 : After reset, these bits are allowed to be changed only once.
Fig. 3.3.7 State of SFR and internal RAM areas immediately after reset (6)
7905 Group User’s Manual Rev.1.0
3-12
RENESAS [ RENESAS TECHNOLOGY CORP ]
