RESET
3.3 State of internal area
Register name
Address
Access characteristics
State immediately after reset
b7
b0
b7
b0
2016
2116
2216
2316
2416
2516
2616
2716
2816
2916
2A16
2B16
2C16
2D16
2E16
2F16
3016
3116
3216
3316
3416
3516
3616
3716
3816
3916
3A16
3B16
3C16
3D16
3E16
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
?
?
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
0
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
0
0
0
0
0
0
?
?
?
?
?
?
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
RW
0
0
0
0
0
0
0
0
0
0016
UART0 transmit/receive mode register
UART0 baud rate register (BRG0)
WO
WO
?
?
?
UART0 transmit buffer register
WO
RW
RO
0
0
0
0
RW
RO
RO
RW
RO
0
0
0
0
0
0
1
0
0
1
0
0
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
RW
RO
?
0
0
0
0
0
0
0
?
UART1 transmit/receive mode register
UART1 baud rate register (BRG1)
RW
WO
WO
0016
?
?
UART1 transmit buffer register
WO
RW
RO
?
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
0
0
0
0
1
0
RW
RO
RO
RW
RO
0
0
0
0
0
0
0
1
0
0
RW
RO
?
UART1 receive buffer register
3F16
0
0
0
0
0
0
0
?
Note 3: The access characteristics at addresses 2016 to 2F16 vary according to the contents of the comparator function
select register 0 (address DC16). (Refer to “CHAPTER 12. A-D CONVERTER.”)
Fig. 3.3.3 State of SFR and internal RAM areas immediately after reset (2)
7905 Group User’s Manual Rev.1.0
3-8
RENESAS [ RENESAS TECHNOLOGY CORP ]
