SERIAL I/O
11.3 Clock synchronous serial I/O mode
The receive operations are described below:
ꢀ The signal input to the RxDi pin is taken into the most significant bit of the UARTi receive register
synchronously with the valid edgeꢀ of the clock output from the CLKi pin or input to the CLKi pin.
ꢀ The contents of the UARTi receive register are shifted, bit by bit, to the right.
ꢀ Steps ꢀ and ꢀ are repeated at each valid edge of the clock output from the CLKi pin or input to the
CLKi pin.
ꢀ When 1-byte data has been prepared in the UARTi receive register, the contents of this register are
transferred to the UARTi receive buffer register.
ꢀ Simultaneously with step ꢀ, the receive complete flag is set to “1.” Additionally, when the receive
interrupt is selected (UARTi receive interrupt mode select bit = “0”), a UARTi receive interrupt request
occurs and its interrupt request bit is set to “1.”
Valid edgeꢀ : A rising edge is selected when the CLK polarity select bit = “0.”
A falling edge is selected when the CLK polarity select bit = “1.”
The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register
is read out. Figure 11.3.11 shows the receive operation, and Figure 11.3.12 shows an example of receive
timing (when an external clock is selected).
When the transfer format select bit is “1” (MSB first), each bit’s position of this register’s contents is
reversed, and then the resultant data is read out.
7905 Group User’s Manual Rev.1.0
11-33
RENESAS [ RENESAS TECHNOLOGY CORP ]
