SERIAL I/O
11.3 Clock synchronous serial I/O mode
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register ← UARTi transmit buffer register.
CTS
i
TCLK
Stopped because transmit enable bit = “0.”
Stopped because CTSi = “H.”
CLK
i
TENDi
D1
D4
D5
D6
D1
D4
D5
D6
D1
D4
D5
D6
D0
D2
D3
D7
D0
D2
D3
D7
D
0
D2
D3
D7
TxD
i
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies when
the following conditions are satisfied:
ꢀ Internal clock selected
T
ENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from the external.)
ꢀ CTS function selected
ꢀ CLK polarity select bit = 0
Tc = TCLK = 2(n+1) /fi
fi: BRGi count source frequency
n: Value set in BRGi
Fig. 11.3.6 Example of transmit timing (when internal clock and CTS function selected)
Tc
Transfer clock
Transmit enable bit
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register←UARTi transmit buffer register.
TCLK
Stopped because transmit enable bit = “0.”
CLKi
TENDi
TxDi
D0 D1 D2 D3 D4 D5
D7 D0 D1 D2 D3 D4 D5
D7
D0 D1 D2 D3 D4 D5
D7
D6
D6
D6
Transmit register
empty flag
UARTi transmit
interrupt request bit
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies
when the following conditions are
satisfied:
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from the external.)
ꢀ Internal clock selected
ꢀ CTS function not selected
ꢀ CLK polarity select bit = 0
Tc = TCLK = 2(n+1) /fi
fi: BRGi count source frequency
n: Value set in BRGi
Fig. 11.3.7 Example of transmit timing (when internal clock selected and CTS function not selected)
7905 Group User’s Manual Rev.1.0
11-28
RENESAS [ RENESAS TECHNOLOGY CORP ]
