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7905 参数 Datasheet PDF下载

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型号: 7905
PDF下载: 下载PDF文件 查看货源
内容描述: 16位单片机 [16-BIT SINGLE-CHIP MICROCOMPUTER]
分类和应用: 计算机
文件页数/大小: 565 页 / 3295 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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SERIAL I/O  
11.3 Clock synchronous serial I/O mode  
11.3.2 Transfer data format  
LSB first or MSB first can be selected as the transfer data format. Table 11.3.3 lists the relationship  
between the transfer data format and writing/reading to and from the UARTi transmit/receive buffer register.  
The transfer format select bit (bit 7 at addresses 3416, 3C16, B416) selects the transfer data format. When  
this bit is cleared to 0,the set data is written to the UARTi transmit buffer register as the transmit data,  
as it is. Similarly, the data in the UARTi receive buffer register is read out as the receive data, as it is.  
(See the upper row in Table 11.3.3.) When this bit is set to 1,each bits position of set data is reversed,  
and the resultant data will be written to the UARTi transmit buffer register as the transmit data. Similarly,  
each bits position of data in the UARTi receive buffer register is reversed, and the resultant data will be  
read out as the receive data. (See the lower row in Table 11.3.3.)  
Note that only the method of writing/reading to and from the UARTi transmit/receive buffer register is  
affected by selection of the transfer data format, and that the transmit/receive operation is unaffected by  
it.  
Table 11.3.3 Relationship between transfer data format and writing/reading to and from UARTi transmit/  
receive buffer register  
Transfer format  
select bit  
Writing to UARTi transmit buffer  
register  
Reading from UARTi receive  
buffer register  
Transfer data format  
Data bus  
UARTi transmit  
buffer register  
Data bus  
UARTi receive  
buffer register  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
7
D
D
D
D
D
D
D
D
7
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
7
D
D
D
D
D
D
D
D
7
6
5
4
3
6
6
5
4
3
2
1
6
5
4
3
2
1
LSB  
(Least Significant Bit)  
first  
5
4
3
2
1
0
0
2
1
0
0
0
Data bus  
UARTi transmit  
buffer register  
Data bus  
UARTi receive  
buffer register  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
7
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
7
D
D
D
D
D
D
D
D
7
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
6
5
4
3
2
1
6
5
4
3
2
1
6
5
4
3
2
1
MSB  
(Most Significant Bit)  
first  
1
0
0
0
0
7905 Group Users Manual Rev.1.0  
11-23  
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