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RTL8201E-VB-GR 参数 Datasheet PDF下载

RTL8201E-VB-GR图片预览
型号: RTL8201E-VB-GR
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, CMOS, PQCC32, GREEN, MO-220, QFN-32]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 44 页 / 796 K
品牌: REALTEK [ Realtek Semiconductor Corp. ]
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RTL8201E(L)  
Datasheet  
Name  
Type  
Pin No. Pin No. Description  
(48-Pin) (32-Pin)  
RXDV  
LI/O/PD  
13  
8
Receive Data Valid.  
This pin’s signal is asserted high when received data is present on the  
RXD[3:0] lines. The signal is de-asserted at the end of the packet. The  
signal is valid on the rising edge of the RXC.  
This pin should be pulled low when operating in MII mode.  
0: MII mode  
1: RMII mode  
An internal weakly pulled low resistor sets this to the default of MII  
mode. It is possible to use an external 4.7Kpulled high resistor to  
enable RMII mode.  
After power on, the pin operates as the Receive Data Valid pin.  
Note: Only the RTL8201E(L)-VB supports RMII mode.  
RXD[0:3]  
O/PD  
14, 16, 9, 10, 11, Receive Data.  
17, 18  
12  
These are the four parallel receive data lines aligned on the nibble  
boundaries driven synchronously to the RXC for reception by the  
external physical unit (PHY).  
RXER/FXEN LI/O/PD  
39  
28  
Receive Error.  
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or  
invalid symbol, this pin will go high.  
Fiber/UTP Enable.  
This pin’s status is latched at power on reset to determine the media  
mode to operate in.  
1: Fiber mode  
0: UTP mode  
An internal weakly pulled low resistor sets this to the default of UTP  
mode. It is possible to use an external 4.7Kpulled high resistor to  
enable fiber mode. After power on, the pin operates as the Receive  
Error pin.  
MDC  
I/PU  
30  
31  
22  
23  
Management Data Clock.  
This pin provides a clock synchronous to MDIO, which may be  
asynchronous to the transmit TXC and receive RXC clocks. The clock  
rate can be up to 2.5MHz. Use an internal weakly pulled high resistor to  
prevent the bus floating.  
MDIO  
IO/PU  
Management Data Input/Output.  
This pin provides the bi-directional signal used to transfer management  
information.  
Single-Chip/Port 10/100 Fast Ethernet PHYceiver  
with Auto MDIX  
7
Track ID: JATR-1076-21 Rev. 1.3