RTL8201CL
Datasheet
3.
Block Diagram
100M
5B 4B
Decoder
Data
Alignment
Descrambler
MII
Interface
RXD
RXC 25M
SNI
Interface
10/100
half/full
Switch
Logic
4B 5B
Encoder
Scrambler
TXD
TXC 25M
10/100M Auto-negotiation
Control Logic
Link pulse
10M
TXC10
TXD10
Manchester coded
waveform
10M Output waveform
shaping
RXC10
RXD10
Data Recovery
Receive low pass filter
TXC 25M
TXD
Parrallel
to Serial
TD+
3 Level
Driver
TXO+
TXO -
Variable Current
Baseline
wander
Correction
MLT-3
to NRZI
3 Level
Comparator
Peak
Detect
Adaptive
Equalizer
RXIN+
RXIN-
RXC 25M
RXD
Serial to
Parrallel
ck
data
Slave
PLL
Master
PPL
Control
Voltage
25M
Figure 1. Block Diagram
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
2
Track ID: JATR-1076-21 Rev. 1.24
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