RTL8201CL
Datasheet
7.5. LED and PHY Address Configuration
In order to reduce the pin count on the RTL8201CL, the LED pins are duplexed with the PHY address
pins. Because the PHYAD strap options share the LED output pins, the external combinations required
for strapping and LED usage must be considered in order to avoid contention. Specifically, when the LED
outputs are used to drive LEDs directly, the active state of each output driver is dependent on the logic
level sampled by the corresponding PHYAD input upon power-up/reset. For example, as Figure 5 (left-
side) shows, if a given PHYAD input is resistively pulled high then the corresponding output will be
configured as an active low driver. On the right side, we can see that if a given PHYAD input is
resistively pulled low then the corresponding output will be configured as an active high driver. The PHY
address configuration pins should not be connected to GND or VCC directly, but must be pulled high or
low through a resistor (ex 5.1KΩ). If no LED indications are needed, the components of the LED path
(LED+510Ω) can be removed.
VCC
PAD[0:4]/
LED[0:4]
LED
LED
5.1K ohm
510 ohm
510 ohm
5.1K ohm
PAD[0:4]/
LED[0:4]
PHY Address[:] = Logical 1
LED Indication = Active low
PHY Address[:] = Logical 0
LED Indication = Active High
Figure 5. LED and PHY Address Configuration
Table 27. LED Definitions
LED Definitions
LED
LED0
LED1
LED2
LED3
LED4
Link
Full Duplex
[CL LED Mode]10-Activity
[CL LED Mode]Fiber/100-Activity
Collision
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
19
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
