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RTL8201CL-VD 参数 Datasheet PDF下载

RTL8201CL-VD图片预览
型号: RTL8201CL-VD
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP48,]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 39 页 / 529 K
品牌: REALTEK [ Realtek Semiconductor Corp. ]
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RTL8201CL  
Datasheet  
7.4. Hardware Configuration and Auto-Negotiation  
This section describes methods to configure the RTL8201CL and set the auto-negotiation mode. Table 26  
shows the various pins and their settings.  
Table 26. Auto-Negotiation Mode Pin Settings  
Pin Name  
Description  
Isolate  
Set high to isolate the RTL8201CL from the MAC. This will also isolate the MDC/MDIO  
management interface. In this mode, power consumption is minimum (see 7.7 Power Down, Link  
Down, Power Saving, and Isolation Modes, page 20).  
RPTR  
Pull high to set the RTL8201CL into repeater mode. This pin is pulled low by default (see  
7.9 Repeater Mode Operation, page 22.  
LDPS  
Pull high to set the RTL8201CL into LDPS mode. This pin is pulled low by default (see 7.7 Power  
Down, Link Down, Power Saving, and Isolation Modes, page 20).  
MII/SNIB  
Pull high to set RTL8201CL into MII mode operation, which is the default mode for the RTL8201.  
This pin pulled low will set the RTL8201CL into SNI mode operation. When set to SNI mode, the  
RTL8201CL will operate at 10Mbps (see 7.6 Serial Network Interface, page 20).  
Auto-Negotiation Enable. Pull high to enable auto-negotiation (default). Pull low to disable auto-  
negotiation and activate the parallel detection mechanism (see 7.2 Auto-Negotiation and Parallel  
Detection, page 16).  
ANE  
SPEED  
DUPLEX  
When ANE is pulled high, the ability to adjust speed is setup. When ANE is pulled low, pull this pin  
low to force 10Mbps operation and high to force 100Mbps operation (see 7.2 Auto-Negotiation and  
Parallel Detection, page 16).  
When ANE is pulled high, the ability to adjust the DUPLEX pin will be setup. When ANE is pulled  
low, pull this pin low to force half duplex and high to force full duplex operation (see 7.2 Auto-  
Negotiation and Parallel Detection, page 16).  
Single-Chip/Port 10/100 Fast Ethernet PHYceiver  
18  
Track ID: JATR-1076-21 Rev. 1.24  
 
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