RTL8201CL
Datasheet
6.10. Register 18 RX_ER Counter (REC)
Table 18. Register 18 RX_ER Counter (REC)
Address
Name
Description
Mode
Default
18:15~0
RXERCNT
This 16-bit counter increments by 1 for each invalid packet
received. The value is valid while a link is established.
RO
H’[0000]
6.11. Register 19 SNR Display Register
Table 19. Register 19 SNR Display Register
Address
Name
Description
Mode
Default
19:15~4
Reserved
Realtek Test Mode Internal use. Do not change this field without
Realtek’s approval.
19:3~0
SNR
These 4-bits show the Signal to Noise Ratio value.
RW
0000
6.12. Register 25 Test Register
Table 20. Register 25 Test Register
Description
Reserved for internal testing.
Address
25:15~12
25:11~7
Name
Test
Mode
RW
RO
Default
PHYAD[4:0] Reflects the PHY address defined by external PHY address
configuration pins.
00001
25:6~2
25:1
Test
LINK10
Reserved for internal testing.
1: 10Base-T link established
0: No 10Base-T link established
1: 100Base-FX or 100Base-TX link established
0: No 100Base link established
RO
RO
0
0
25:0
LINK100
RO
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
13
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
