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RTL8201CL-VD 参数 Datasheet PDF下载

RTL8201CL-VD图片预览
型号: RTL8201CL-VD
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP48,]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 39 页 / 529 K
品牌: REALTEK [ Realtek Semiconductor Corp. ]
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RTL8201CL  
Datasheet  
6.8. Register 16 NWay Setup Register (NSR)  
Table 16. Register 16 NWay Setup Register (NSR)  
Address  
16:15~12  
16:11  
16:10  
16:9  
16:8~3  
16:2  
16:1  
Name  
Description  
Mode  
Default  
Reserved  
ENNWLE  
Testfun  
NWLPBK  
Reserved  
FLAGABD  
FLAGPDF  
FLAGLSC  
1: LED4 Pin indicates linkpulse  
1: Auto-negotiation speeds up internal timer  
1: Set NWay to loopback mode  
RW  
RW  
RW  
0
0
0
1: Auto-negotiation experienced ability detect state  
1: Auto-negotiation experienced parallel detection fault state  
1: Auto-negotiation experienced link status check state  
RO  
RO  
RO  
0
0
0
16:0  
6.9. Register 17 Loopback, Bypass, Receiver Error Mask  
Register (LBREMR)  
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR)  
Address  
17:15  
17:14  
Name  
RPTR  
BP_4B5B  
Description  
Mode  
RW  
RW  
Default  
Set to 1 to put the RTL8201CL into repeater mode.  
Assertion of this bit allows bypassing of the 4B/5B & 5B/4B  
encoder.  
0
0
17:13  
BP_SCR  
Assertion of this bit allows bypassing of the  
scrambler/descrambler.  
RW  
0
17:12  
17:11  
LDPS  
AnalogOFF  
Set to 1 to enable Link Down Power Saving mode.  
Set to 1 to power down analog function of transmitter and  
receiver.  
RW  
RW  
0
0
17:10  
17:9  
17:8  
17:7  
17:6  
17:5  
17:4  
Reserve  
LB  
F_Link_10  
F_Link_100  
JBEN  
Reserved.  
Set to 1 to enable DSP Loopback.  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
1
1
0
0
Used to logic force good link in 10Mbps for diagnostic purposes.  
Used to logic force good link in 100Mbps for diagnostic purposes.  
Set to 1 to enable Jabber Function in 10Base-T.  
Assertion of this bit causes a code error detection to be reported.  
Assertion of this bit causes a pre-mature end error detection to be  
reported.  
CODE_err  
PME_err  
17:3  
17:2  
LINK_err  
PKT_err  
Assertion of this bit causes a link error detection to be reported.  
Assertion of this bit causes a ‘detection of packet errors due to  
722 ms time-out’ to be reported.  
RW  
RW  
0
0
17:1  
17:0  
FXMODE  
RMIIMODE  
This bit indicates whether Fiber Mode is Enabled.  
This bit indicates whether RMII mode is Enabled.  
RO  
RO  
0
0
Single-Chip/Port 10/100 Fast Ethernet PHYceiver  
12  
Track ID: JATR-1076-21 Rev. 1.24  
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