RTL8201CL
Datasheet
6. Register Descriptions
This section describes the functions and usage of the registers available in the RTL8201CL.
In this section the following abbreviations are used:
RO: Read Only
RW: Read/Write
6.1. Register 0 Basic Mode Control Register
Table 9. Register 0 Basic Mode Control Register
Address
Name
Description
Mode
Default
0:15
Reset
This bit sets the status and control registers of the PHY in a default
state. This bit is self-clearing.
RW
0
1: Software reset
0: Normal operation
0:14
0:13
Loopback This bit enables loopback of transmit data nibbles TXD3:0 to the
RW
RW
0
0
receive data path.
1: Enable loopback
0: Normal operation
Spd_Set
This bit sets the network speed.
1: 100Mbps
0: 10Mbps
After completing auto negotiation, this bit will reflect the Speed status.
1: 100Base-T
0: 10Base-T)
When 100Base-FX mode is enabled, this bit=1 and is read only.
0:12
0:11
Auto
This bit enables/disables the NWay auto-negotiation function.
RW
RW
1
0
Negotiation 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored.
Enable
0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the link
speed and the data transfer mode, respectively.
When 100Base-FX mode is enabled, this bit=0 and is read only.
Power Down This bit turns down the power of the PHY chip, including the internal
crystal oscillator circuit. The MDC, MDIO is still alive for accessing
the MAC.
1: Power down
0: Normal operation
0:10
0:9
Reserved
Restart Auto This bits allows the NWay auto-negotiation function to be reset.
Negotiation 1: Re-start auto-negotiation
0: Normal operation
RW
RW
0
0
0:8
Duplex
Mode
This bit sets the duplex mode if auto-negotiation is disabled
(bit 0:12=0).
1: Full duplex
0: Half duplex
After completing auto-negotiation, this bit will reflect the duplex
status.
1: Full duplex
0: Half duplex
0:7:0
Reserved
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
8
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
