VRS51L1050
ISP Program Start Conditions
Setting the ISP page configuration to a value other
than 0 will cause the processor to jump to the base
address of the ISP boot code when a hardware reset is
performed (provided that the value FFh is present at
program address 0000h).
When the ISP page configuration is set to 0 at the
moment the device is programmed using a parallel
programmer, the ISP boot feature will be disabled.
An alternate way to force the VRS51C1050 to jump to
the ISP boot program is to maintain pins P2.6 and
P2.7 or pin P4.3 at a low logic level during a hardware
reset, as shown in the diagram below:
F
IGURE
5: VRS51C1050 A
LTERNATE
ISP
BOOT PROGRAM ACCESS
10ms
10ms
VRS51L1050 IAP feature
The VRS51L1050 IAP feature refers to the processor’s
ability to self-program the Flash memory from within
the user program. Five SFR registers control the IAP
operation. The description of these registers is
provided in the following sections.
System Control Register
By default, upon reset the IAP feature of the
VRS51L1050 is deactivated. The IAPE bit of the
SYSCON register is used to enable (and disable) the
VRS51L1050 IAP function.
T
ABLE
6: S
YSTEM
C
ONTROL
R
EGISTER
(SYSCON) – SFR BF
H
7
6
5
4
PDWAKEU
P
3
2
IAPE
1
XRAME
0
ALEI
P2.7
Bit
7
6
5
4
Mnemonic
Unused
Unused
Unused
PDWAKEUP
P2.6
RES
3
2
1
Unused
IAPE
XRAME
ALEI
OR...
0
10ms
10ms
Description
-
-
-
Power down wakeup from INT0 / INT1
0 = Deactivated
1 = Device can wakeup from power down
from external interrupt
-
IAP function enable bit
0 = IAP function is deactivated
1 = IAP function is activated
768 byte on-chip enable bit
0 = Enabled
1 = Disabled
ALE output inhibit bit, used to reduce EMI.
0 = ALE pin is active
1 = ALE is inhibited
P4.3
IAP Flash Address and Data Registers
The IAPFADHI and IAPADLO registers are used to
specify the address at which the IAP function will be
performed.
T
ABLE
7:IAP F
LASH
A
DDRESS
H
IGH
- SFR F4
H
RES
The ISP boot program can also be accessed via the
LJMP instruction. When the ISP page configuration is
set to 0 while the device is being programmed with a
parallel programmer, the ISP boot feature will be
disabled.
7
6
5
4
3
2
IAPFADHI[15:8]
4
3
2
IAPFADLO[15:8]
1
0
T
ABLE
8:IAP F
LASH
A
DDRESS
L
OW
- SFR F5
H
7
6
5
1
0
The IAPFDATA SFR register contains the data byte
required to perform the IAP function.
T
ABLE
9:IAP F
LASH
D
ATA
R
EGISTER
- SFR F6
H
7
6
5
4
3
2
IAPFDATA[7:0]
1
0
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