VRS51C1000
VRS51C1000 ISPVx Firmware boot program
An ISP boot loader program is available for the
VRS51C1000 (ISPVx Firmware, x = revision, see
Ramtron website for latest revision).
The ISPVx Firmware enables In-System-Programming
of the VRS51C1000 on the final application PCB using
the device’s UART interface. See the following figure
for a hardware configuration example.
Other
configurations are also possible.
F
IGURE
4: VRS51C1000 I
NTERFACE FOR
I
N
-S
YSTEM
P
ROGRAMMING
System Control Register
By default upon reset, the IAP feature of the
VRS51C1000 is de-activated. The IAPE bit of the
SYSCON register is used to enable (and disable) the
VRS51C1000 IAP function.
T
ABLE
6: S
YSTEM
C
ONTROL
R
EGISTER
(SYSCON) – SFR BF
H
7
WDR
Bit
7
6
5
4
Unused
3
2
IAPE
1
XRAME
0
ALEI
Mnemonic
WDR
Unused
Unused
Unused
Unused
IAPE
XRAME
ALEI
VRS51C1000
RS232 Transceiver
(with ISPV2
Firmware)
TXD
To PC
RXD
PNP
150k
Creset
RES
6
5
4
3
2
1
0
Description
This is the Watchdog Timer reset bit. It will
be set to 1 when the reset signal generated
by WDT overflows.
-
-
-
-
IAP function enable bit
768 byte on-chip enable bit
ALE output inhibit bit, which is used to
reduce EMI.
RS232 interf.
51k
IAP Flash Address and Data Registers
Rreset
See Ramtron’s website in order to download the
“Versa Ware ISP” Window’s™ application which allows
communication with the ISPVx firmware.
The VRS51C1000 can be ordered with or without the
ISPVx bootloader firmware (see Ordering information
section of this Datasheet for part number information).
The ISPVx bootloader firmware can also be
programmed into the VRS51C1000 by the user.
Source code is included with the Versa Ware ISP
application software.
For more information on the ISPVx firmware, please
consult the “VRS51C1000 ISPVx Firmware User
Guide.pdf” available on the Ramtron web site.
The IAPFADHI and IAPADLO registers are used to
specify the address at which the IAP function will be
performed.
T
ABLE
7:IAP F
LASH
A
DDRESS
H
IGH
- SFR F4
H
7
6
5
4
3
2
IAPFADHI[15:8]
1
0
T
ABLE
8:IAP F
LASH
A
DDRESS
L
OW
- SFR F5
H
7
6
5
4
3
2
IAPFADLO[15:8]
1
0
The IAPFDATA SFR register contains the Data byte
required to perform the IAP function.
T
ABLE
9:IAP F
LASH
D
ATA
R
EGISTER
- SFR F6
H
7
6
5
4
3
2
IAPFDATA[7:0]
1
0
IAP Flash Control Register
The VRS51C1000 IAP function operation is controlled
by the IAP Flash Control register, IAPFCTRL.
Setting the IAPSTART bit to 1, starts the execution of
the IAP command specified by the IAPFCT[1:0] bits of
the IAP Flash Control register.
VRS51C1000 IAP feature
The VRS51C1000 IAP feature refers to the ability of
the processor to self-program the Flash memory from
within the user program.
Five SFR registers serve to control the IAP operation.
The description of these registers is provided below.
______________________________________________________________________________________________
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