72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
TAP DC Electrical Characteristics
Symbol
VOH1
VOH2
VOL1
VOL2
VIH
Parameter
Output High Voltage
Test Conditions
IOH = -2.0 mA
IOH = -100 µA
IOL = 2.0 mA
IOL = 100 µA
−
Min
2.0
2.2
-
Max
Units
V
Notes
-
-
1
1
Output High Voltage
Output Low Voltage
V
0.4
V
1
Output Low Voltage
-
0.2
V
1
Input High Voltage
1.7
-0.3
-
VDD+0.3
0.7
V
1, 2
1, 2
1
VIL
Input Low Voltage
V
−
IX
Input and Output Leakage Current
GND ≤ VIN ≤ VDDQ
±5
µA
Notes:
1. All voltage referenced to ground.
2. Overshoot: VIH(AC) ≤ VDD+0.7V for t ≤ (tTCYC / 2),
Undershoot: VIL(AC) ≤ 0.5V for t ≤ (tTCYC / 2),
Power up: VIH ≤ 2.6V and VDD<2.4V and VDDQ<1.4 for t<200ms.
TAP AC Switching Characteristics
Symbol
tTCYC
tTF
Parameter
Min
100
-
Max
Units
ns
Notes
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock High
-
10
-
1
1
MHz
ns
tTH
40
40
10
10
10
10
10
10
-
1
tTL
TCK Clock Low
-
ns
1
tTMSS
tTDIS
tCS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Clock Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
-
ns
1
-
ns
1
-
ns
1, 2
1
tTMSH
tTDIH
tCH
-
ns
-
ns
1
Capture Hold after Clock Rise
TCK Clock Low to TDO Valid
TCK Clock Low to TDO Invalid
-
ns
1, 2
1
tTDOV
tTDOX
20
-
ns
0
ns
1
Notes:
1. Test conditions are specified using the loads in TAP AC test conditions. tR/tF = 1 ns.
2. CS and tCH refer to the setup and hold time requirements for latching data from the Boundary Scan register.
t
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 22 of 30
Revision 1.0
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
