72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
Scan Register Sizes
Register Name
Instruction
Bypass
Bit Size
3
1
ID
32
70
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input/output states. Places the Boundary Scan register
between TDI and TDO. Forces all SRAM outputs to high-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
Captures the input/output states. Places the Boundary Scan register
between TDI and TDO. Forces all SRAM output drivers to a high-Z state
RESERVED
011
100
Do Not Use: This instruction id reserved for future use.
SAMPLE/PRELOAD
Captures the input/output states. Places the Boundary Scan register
between TDI and TDO. Does not affect SRAM operation. This instruction
does not implement the 1149.1 preload function and is therefore not
1149.1 compliant
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction id reserved for future use.
Do Not Use: This instruction id reserved for future use.
Places the Bypass register between TDI and TDO. Does not affect
SRAM operation.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 26 of 30
Revision 1.0
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
