72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
TAP Timing and Test Conditions
1.25V
All Input Pulses
50
Ω
2.5V
0 V
1.25V
TDO
Z0 = 50
Ω
CL = 20 pF
tTCYC
tTH
tTL
Test Clock
TCK
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
tTDOV
tTDOX
Test Data-Out
TDO
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
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