72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
TAP Instruction Set
Eight different instructions are possible with the 3-bit Instruction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are
described below.
The TAP controller used in this SRAM is not fully compliant with the 1149.1 conventions because some of the mandatory
instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the
SRAM, and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 instructions EXTEST,
INTEST, or the PRELOAD portion of SAMPLE/PRELOAD. Instead it capture the current states on the inputs and
outputs of the pad ring when these instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR state when the Instruction register is placed between
TDI and TDO. During this state, instructions are shifted through the Instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP controller is moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction that is executed when the Instruction register is loaded with all 0s.
EXTEST, as specified, is not implemented in the TAP controller. Therefore, this device is not fully compliant with the
1149.1 standard.
However, the TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the
Instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction is loaded. The only difference is that
unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a high-Z state.
IDCODE
The IDCODE instruction causes a vendor specific, 32-bit code to load into the ID register. It also places the ID register
between the TDI and TDO pins, and allows shifting of the IDCODE out of the device when the TAP controller enters
the Shift-DR state. The IDCODE instruction is loaded into the Instruction register at power up or when the TAP
controller is given a TEST-LOGIC RESET state.
SAMPLE-Z
The SAMPLE-Z instruction places the Boundary Scan register between the TDI and TDO pins when the TAP
controller enters a Shift-DR state. It also places all SRAM outputs into a high-Z state.
SAMPLE/PRELOAD
SAMPLE/Preload is a mandatory 1149.1 instruction. The PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully compliant with the 1149.1 standard.
When the SAMPLE/PRELOAD instruction is loaded into the Instruction register, and the TAP controller is in the
Capture-DR state, a snapshot of data on the input and output pins is captured in the Boundary Scan register.
An important point is that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock
operates more that a magnitude faster. Because of this, it is possible for an input or output to change during the
Capture-DR state. If the TAP tries to capture a signal while it is transitioning (metastable state), the device is not
harmed, but the results are not guaranteed and possibly not repeatable.
To guarantee that the Boundary Scan register captures the correct value, the signal must be stable long enough to meet
TAP controller capture set-up and hold times (tCS and tCH). To capture the SRAM clock input correctly there must be a
way to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is not done in the design, it is still
possible to capture all other signals and simply ignore the value of CLK captured in the Boundary Scan register.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
Copyright 2001 Enhanced Memory Systems. All rights reserved.
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
The information contained herein is subject to change without notice.
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Revision 1.0
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
