64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Read/Write/Read (CL = 1, BL = 4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRCD
tRCD
tDPL
tRP
tRAS
tRP
CS#
RAS#
CAS#
WE#
Bo
R0
R0
R0
B0
C0
B0
C0
B0
B0
C4
BA(1:0)
A11, A9
A10/AP
A(8:0)
DQM
R1
R1
R1
Q0
Q1
Q2
Q3
D0
D1
D2
D3
Q4
Q5
Q6
Q7
DQ
Internal Status
Bank 0
Active
Pre
Active
Pre
Idle
* * * *
R0
R1
Cache 0
Cache modified at column addresses.
*
This pattern shows the SRAM row cache being loaded by a Read command while the DRAM remains active. A write
follows, and the data on the DQ bus is used to update both the DRAM bank and the SRAM row cache at column
addresses C0 - C4. The SRAM row cache is otherwise undisturbed. A read from row 1 is shown to illustrate the earliest
time bank 0 can be re-activated.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Revision 1.1
Page 25 of 33
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
