64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Burst Writes (BL = 4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CLK
tRCD
tDPL
tRP
tRCD
tDPL
tRP
tRAS
tRAS
tRC
CS#
RAS#
CAS#
WE#
B0
B0
B0
B0
B0
BA(1:0)
A11, A9
A10/AP
A(8:0)
DQM
R0
R0
R0
R1
R1
R1
C0
D0
C4
D4
C0
D0
D1
D2
D3
D5
D6
D7
D1
D2
D3
DQ
Internal Status
Bank 0
Active
Precharge
Active
Precharge
Idle
* * * * * * * *
R0
R1
Cache 0
Cache modified at column addresses.
*
This diagram shows two burst writes to row 0 followed by a burst write to row 1. Once the DRAM bank is activated, the
Write command caches the row. Data on the DQ bus is used to update both the SRAM row cache and the DRAM bank at
the column addresses specified. At frequencies below 83 MHz, the tRCD and tRP times can be reduced to one clock cycle.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Page 24 of 33
Revision 1.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
