64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Burst Reads (CL = 1, BL = 4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRCD
tRP
tRCD
tRP
tRAS
tRAS
tRC
CS#
RAS#
CAS#
WE#
B0
R0
R0
R0
B0
C0
B0
R1
R1
R1
B0
B0
BA(1:0)
A11, A9
A10/AP
A(8:0)
DQM
C4
Q3
C8
Q7
Q0
Q1
R0
Q2
Q4
Q5
Q6
Q8
Q9
Q10
Q11
DQ
Internal Status
Bank 0
Active
Pre
Idle
Active
Pre
Idle
R1
Cache 0
In CL1 mode the ESDRAM can perform burst reads without wait states. The timing shown is a worst-case situation in
which a read from row 0 is followed by a read from row 1, both in bank 0. The row cache is loaded on the Read command
and the DRAM bank is auto-precharged one clock cycle following the Read command. Once the precharge time tRP is
satisfied, the DRAM bank is idle and can be re-activated or refreshed.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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Revision 1.1