64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Burst Termination (BL = 4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CS#
RAS#
CAS#
WE#
B0
R0
R0
R0
B0
C0
B0
B0
C4
B1
B0
BA(1:0)
A11, A9
A10/AP
A(8:0)
C8
Q7
DQM
Q0
Q1
Q0
Q4
Q5
Q4
Q6
Q7
Q8
Q9
Q10
DQ (CL1)
DQ (CL2)
Q1
Q5
Q6
Q8
Q9
Q10
Internal Status
Bank 0
Active
Precharge
Idle
Active
Precharge
Idle
Bank 1
For burst reads, the Precharge and Burst Termination commands hi-Z the DQ bus in CL clock cycles. A single bank Pre-
Charge command to a bank that is not bursting pre-charges that bank, but does not terminate the other bank’s burst. For
burst writes, the Precharge and Burst Termination commands terminate the burst in the same clock cycle in which the
command is registered by the ESDRAM.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Page 28 of 33
Revision 1.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
