64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
AC Characteristics (TA = 0°C to 70°C, VDD = 3.3V +10%, -5%)
1. After power is applied to VDD and VDDQ (simultaneously) and the clock is stable, an initial pause of 100µs is required.
After the 100µs delay is satisfied and at least one DESEL or NOP is applied, a Precharge All Banks command must
be given followed by a minimum of two Auto (CBR) Refresh cycles before the Mode Register Set operation can
begin.
2. For VDDQ = 3.3V, AC timing and IDD tests have VIL = 0V and VIH = 2.8V with the timing referenced to the VTT = 1.4V
crossover point.
tT
VT T
VIH
VIL
1.4V
Clock
tSETUP tHOLD
RT = 50 ohm
CLOAD = 50pF
Z0 = 50 ohm
Input
Output
Output
VT T
tLZ
tOH
tAC
AC Output Load Curcuit
3. AC measurements assume tT = 1ns and one address transition per clock cycle.
4. In addition to meeting the transition rate specification, the clock and CKE must transition VIH and VIL (or between VIH
and VIL) in a monotonic manner.
5. The CLOAD value for the –6 speed grade is 30pF.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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Revision 1.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
