FM33256/FM3316 SPI Companion w/ FRAM
3
4
tDOG1 is the programmed StartTime and tDOG2 is the programmed EndTime in registers 0Bh and 0Ch, VDD > VTP, and tRPU
satisfied. The StartTime has a resolution of 25ms. The EndTime has a resolution of 60ms.
The /RST pin will drive low for this amount of time after the internal reset circuit is activated due to a watchdog, low
voltage, or manual reset event.
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.0V)
Symbol
CIO
CXTL
Parameter
Input/Output Capacitance
X1, X2 Crystal pin Capacitance
Typ
Max
8
-
Units
pF
pF
Notes
1
1, 2
-
25
-
CCNT
Max. Allowable Capacitance on CNT (polled mode)
100
pF
Notes
1
This parameter is characterized but not tested.
2
The crystal attached to the X1/X2 pins must be rated as 12.5pF.
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Min
Units
Notes
Data Retention
10
Years
AC Test Conditions
Input Pulse Levels
10% and 90% of VDD
Input Rise and Fall Times
Input and Output Timing Levels
Output (SO) Load Capacitance
5 ns
0.5 VDD
30 pF
Diagram Notes
All timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write
timing parameters apply to op-code, word address, and write data bits. Functional relationships are illustrated in the relevant data
sheet sections. These diagrams illustrate the timing parameters only.
Serial Data Bus Timing
tD
CS
tCL
tCH
tF
tR
tCSH
tCSU
1/tCK
SCK
SI
tH
tSU
tOH
tOD
tODV
SO
Rev. 1.0
Dec. 2006
Page 25 of 28
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
