FM33256/FM3316 SPI Companion w/ FRAM
After the op-code and address are issued, the device
drives out the read data on the next 8 clocks. The SI
input is ignored during read data bytes. Subsequent
bytes are data bytes, which are read out sequentially.
Addresses are incremented internally as long as the
bus master continues to issue clocks and /CS is low.
If the last address is reached (e.g. 7FFFh on the
FM33256), the counter will roll over to 0000h. Data
is read MSB first. The rising edge of /CS terminates a
READ operation. A read operation is shown in
Figure 20.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
6
7
0
1
6
2
5
3
4
3
5
2
6
1
7
7
SCK
16-bit Address
12 11
Data In
4
Op-code
SI
0
0
0
1
0
X
14
13
1
0
7
0
0
0
0
0
MSB
LSB MSB
LSB
Hi-Z
SO
Figure 19. Memory Write
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
7
7
SCK
16-bit Address
12 11
Op-code
0
SI
0
0
0
1
1
X
14
13
1
0
0
0
MSB
LSB
Data Out
4
Hi-Z
SO
7
6
5
3
2
1
0
0
MSB
LSB
Figure 20. Memory Read
Addressing FRAM Array in the FM33xx Family
The FM33xx devices include 256Kb and 16Kb memory densities. The following 2-byte address field is shown for
each density.
Table 7. Two-Byte Memory Address
Part #
FM33256
FM3316
1st Address Byte
2nd Address Byte
x
x
A14 A13 A12 A11 A10
A9
A9
A8
A8
A7
A7
A6
A6
A5
A4
A3
A2
A1
A1
A0
A0
x
x
x
x
A10
A5
A4
A3
A2
Rev. 1.0
Dec. 2006
Page 22 of 28
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
