FM33256/FM3316 SPI Companion w/ FRAM
DC Operating Conditions, continued (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units Notes
VOL
VOH
Output Low Voltage @ IOL = 3 mA
Output High Voltage
-
0.4
V
(SO, PFO) @ IOH = -2 mA
VDD – 0.8
50
1.475
-
V
KΩ
V
RRST
VPFI
VHYS
Notes
Pull-up resistance for /RST inactive
Power Fail Input Reference Voltage
Power Fail Input (PFI) Hysteresis (Rising)
400
1.525
100
1.50
-
mV
1. Full complete operation. Supervisory circuits, RTC, etc operate to lower voltages as specified.
2. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
3. All inputs at VSS or VDD, static. Trickle charger off (VBC=0).
4. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications.
5. VBAK = 3.0V, VDD < VSW, oscillator running, CNT at VBAK.
6. VBAK will source current when trickle charge is enabled (VBC bit=1), VDD > VBAK, and VBAK < VBAK max.
7. This is the VDD supply current contributed by enabling the trickle charger circuit, and does not account for IBAKTC
8. This is the VDD supply current contributed by enabling the watchdog circuit, WDE=1 and WDET set to a non-zero value.
9. /RST is asserted active when VDD < VTP
.
.
10. The minimum VDD to guarantee the level of /RST remains a valid VOL level.
11. VIN or VOUT = VSS to VDD. Does not apply to PFI, X1, or X2.
12. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM33xx.
AC Parameters (TA = -40°C to + 85°C, VDD = 2.7V to 3.6V CL = 30 pF)
Symbol
fCK
tCH
tCL
tCSU
tCSH
tOD
tODV
tOH
tD
Parameter
Min
0
28
28
10
10
Max
16
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Notes
SCK Clock Frequency
Clock High Time
Clock Low Time
Chip Select Setup
Chip Select Hold
Output Disable Time
Output Data Valid Time
Output Hold Time
Deselect Time
1
1
20
24
2
0
90
ns
tR
tF
tSU
tH
Data In Rise Time
Data In Fall Time
Data Setup Time
Data Hold Time
50
50
ns
ns
ns
ns
1,3
1,3
6
6
Notes
1. tCH + tCL = 1/fCK
.
2. This parameter is characterized but not 100% tested.
3. Rise and fall times measured between 10% and 90% of waveform.
Supervisor Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V)
Symbol
tRPW
tRNR
tVR
tVF
tWDST
tWDET
fCNT
Parameter
/RST Pulse Width (active low time)
/RST Response Time to VDD<VTP (noise filter)
VDD Rise Time
VDD Fall Time
Watchdog StartTime
Min
30
7
50
100
0.3*tDOG1
tDOG2
0
Max
100
25
-
-
tDOG1
3.3*tDOG2
1
Units
ms
µs
µs/V
µs/V
ms
Notes
1
1,2
1,2
3
Watchdog EndTime
Frequency of Event Counter
ms
kHz
3
Notes
1
This parameter is characterized but not tested.
2
Slope measured at any point on VDD waveform.
Rev. 1.0
Dec. 2006
Page 24 of 28
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
