FM33256/FM3316 SPI Companion w/ FRAM
CS
0
1
2
3
4
5
0
6
1
7
0
0
1
2
3
4
5
6
1
7
0
0
7
1
6
2
5
3
4
5
2
6
1
7
7
SCK
op-code
Register Address
Data
SI
0
0
0
1
0
7
6
5
4
3
2
4
3
0
0
MSB
LSB
LSB MSB
LSB
SO
Hi-Z
Figure 18. Processor Companion Write
Status Register & Write Protection
Memory Operation
The write protection features of the FM33xx are
multi-tiered. To write the memory, a WREN op-code
must first be issued, followed by a WRITE op-code.
A Status Register associated with the memory has a
write enable latch bit (WEL) that is internally set
when WREN is issued.
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the FRAM technology. Unlike SPI-bus
EEPROMs, the FM33xx can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Writes to certain memory blocks are controlled by
the Block Protect bits in the Status Register. The BP
bits may be changed by using the WRSR command.
The Status Register is organized as follows.
Write Operation
All writes to the memory begin with a WREN op-
code with /CS being asserted and deasserted. The
next op-code is a WRITE. The WRITE op-code is
followed by a two-byte address value. Table 7 shows
the addressing scheme for each density. This is the
starting address of the first data byte of the write
operation. Subsequent bytes are data bytes, which are
written sequentially. Addresses are incremented
internally as long as the bus master continues to issue
clocks and keeps /CS low. A write operation will be
terminated when a write-protected address is directly
accessed or when the device has internally
incremented the address into a write-protected space.
If the last address is reached (e.g. 7FFFh on the
FM33256), the counter will roll over to 0000h. Data
is written MSB first. The rising edge of /CS
terminates a WRITE operation. A write operation is
shown in Figure 19. Note: Although the WREN op-
code is not shown in the timing diagram, it is
required prior to sending the WRITE command.
Table 5. Status Register
Bit
7
0
6
1
5
0
4
0
3
BP1
2
BP0
1
0
0
Name
WEL
Bits 7, 5, 4, and 0 are fixed at 0, bit 6 is fixed at 1,
and none of these bits can be modified. Note that bit
0 (Ready in EEPROMs) is unnecessary as the FRAM
writes in real-time and is never busy. The BP1 and
BP0 control software write-protection features. They
are nonvolatile (shaded yellow). The WEL flag
indicates the state of the Write Enable Latch.
Attempting to directly write the WEL bit in the Status
Register has no effect on its state, since this bit is
internally set and cleared via the WREN and WRDI
commands, respectively. BP1 and BP0 are memory
block write protection bits. They specify portions of
memory that are write-protected as shown in the
following table.
EEPROMs use page buffers to increase their write
throughput. This compensates for the technology’s
inherently slow write operations. FRAM memories
do not have page buffers because each byte is written
to the FRAM array immediately after it is clocked in
(after the 8th clock). This allows any number of bytes
to be written without page buffer delays.
Table 6. Block Memory Write Protection
BP1
BP0
Protected Address Range
0
0
1
1
0
1
0
1
None
Upper ¼
Upper ½
All
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following the READ command is
a two-byte address value. Table 7 shows the
addressing scheme for each density. This is the
starting address of the first byte of the read operation.
Rev. 1.0
Dec. 2006
Page 21 of 28
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
