FM28V020 - 32Kx8 F-RAM
Overview
The FM28V020 is a bytewide F-RAM memory
logically organized as 32,768 x 8 and is accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page is triggered
by toggling the chip enable pin or simply by changing
the upper address A(14:3).
write. The FM28V020 will not drive the data bus
regardless of the state of /OE as long as /WE is low.
Input data must be valid when the device is
deselected with the chip enable. In a /WE-controlled
write, the memory cycle begins when the device is
activated with the chip enable. The /WE signal falls
some time later. Therefore, the memory cycle begins
as a read. The data bus will be driven if /OE is low,
however it will hi-Z once /WE is asserted low. The
/CE- and /WE-controlled write timing cases are
shown on page 9. In the
Write Cycle Timing 2
diagram, the data bus is shown as a hi-Z condition
while the chip is write-enabled and before the
required setup time. Although this is drawn to look
like a mid-level voltage, it is recommended that all
DQ pins comply with the minimum V
IH
/V
IL
operating
levels.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the deassertion of /WE or /CE,
whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE or /CE. Data setup time
indicates the interval during which data cannot
change prior to the end of the write access.
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The FM28V020 provides the user fast access to any
data within a row element. Each row has eight
column locations. An access can start anywhere
within a row and other column locations may be
accessed without the need to toggle the /CE pin. For
page mode reads, once the first data byte is driven
onto the bus, the column address inputs A(2:0) may
be changed to a new value. A new data byte is then
driven to the DQ pins. For page mode writes, the
first write pulse defines the first write access. While
the device is selected (/CE low), a subsequent write
pulse along with a new column address provides a
page mode write access.
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is preparing for a new
access. Precharge is user-initiated by driving at least
one of the chip enable signals to an inactive state. The
Page 4 of 14
Memory Operation
Users access 32,768 memory locations with 8 data
bits each through a parallel interface. The F-RAM
array is organized as 8 blocks each having 512 rows.
Each row has 8 column locations, which allows fast
access in page mode operation. Once an initial
address has been latched by the falling edge of /CE,
subsequent column locations may be accessed
without the need to toggle the chip enable. When
either chip enable pin is deasserted, a precharge
operation begins. Writes occur immediately at the end
of the access with no delay. The /WE pin must be
toggled for each write operation.
Read Operation
A read operation begins on the falling edge of /CE.
The /CE-initiated access causes the address to be
latched and starts a memory read cycle if /WE is high.
Data becomes available on the bus after the access
time has been satisfied. Once the address has been
latched and the access completed, a new access to a
random location (different row) may begin while /CE
is still active. The minimum cycle time for random
addresses is t
RC
. Note that unlike SRAMs, the
FM28V020’s /CE-initiated access time is faster than
the address cycle time.
The FM28V020 will drive the data bus only when
/OE is asserted low and the memory access time has
been satisfied. If /OE is asserted prior to completion
of the memory access, the data bus will not be driven
until valid data is available. This feature minimizes
supply current in the system by eliminating transients
caused by invalid data being driven onto the bus.
When /OE is inactive, the data bus will remain hi-Z.
Write Operation
Writes occur in the FM28V020 in the same time
interval as reads. The FM28V020 supports both /CE-
and /WE-controlled write cycles. In both cases, the
address is latched on the falling edge of /CE.
In a CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when the device is activated with the chip enable.
In this case, the device begins the memory cycle as a
Rev. 2.1
June 2011
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
