FM25W256 - 256Kb SPI F-RAM
CS
0
SCK
Op-code
0
Hi-Z
16-bit Address
0
0
1
0
X
MSB
14
13
12
11
1
0
LSB
7
MSB
6
5
Data In
4
3
2
1
0
LSB
0
1
2
3
4
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
7
7
SI
SO
0
0
0
Figure 9. Memory Write
(WREN must precede WRITE)
CS
0
SCK
Op-code
0
Hi-Z
16-bit Address
0
0
1
1
X
MSB
14
13
12
11
1
0
LSB
7
MSB
6
5
Data Out
4
3
2
1
0
LSB
0
1
2
3
4
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
7
7
SI
SO
0
0
0
Figure 10. Memory Read
Endurance
The FM25W256 device is capable of operating at
least 10
14
read or write cycles. A F-RAM memory
operates with a read and restore mechanism.
Therefore, an endurance cycle is applied on a row
basis for each access (read or write) to the memory
array. The F-RAM architecture is based on an array
of rows and columns. Rows are defined by A14-A3
and column addresses by A2-A0.
See Block
Diagram (pg 2) which shows the array as 4K rows of
64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 20MHz clock rate.
Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop
SCK Freq
Endurance
Endurance
Years to Reach
(MHz)
Cycles/sec.
Cycles/year
10
14
Cycles
20
37,310
1.18 x 10
12
85.1
11
10
18,660
5.88 x 10
170.2
11
5
9,330
2.94 x 10
340.3
Rev. 1.3
Feb. 2011
Page 8 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
