FM25W256 - 256Kb SPI F-RAM
Serial Data Bus Timing
/HOLD Timing
tHS
S
tHH
C
tHH
tHS
HOLD
Q
tHZ
tLZ
Power Cycle Timing
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V unless otherwise specified)
Symbol
tPU
Parameter
Min
10
Max
Units
ms
Notes
VDD(min) to First Access Start
-
-
-
-
tPD
Last Access Complete to VDD(min)
VDD Rise Time
0
µs
tVR
tVF
Notes
30
100
1
1
µs/V
µs/V
VDD Fall Time
1. Slope measured at any point on VDD waveform.
Rev. 1.3
Feb. 2011
Page 11 of 13