FM25L16B - 16Kb 3V SPI F-RAM
CS
0
SCK
op-code
SI
SO
0
0
0
0
0
0
1
0
X
MSB
X
11-bit Address
X X X 10 9
3
2
1
0
7
6
Data
5 4
3
2
1
0
LSB
1
2
3
4
5
6
7
0
1
2
3
4
5
6
4
5
6
7
0
1
2
3
4
5
6
7
LSB MSB
Figure 9. Memory Write (WREN not shown)
CS
0
SCK
op-code
SI
0
0
0
0
0
0
1
1
X
MSB
SO
X
11-bit Address
X X X 10 9
3
2
1
0
LSB
MSB
7
6
5
Data
4
3
2
1
LSB
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
4
5
6
7
0
1
2
3
4
5
6
7
Figure 10. Memory Read
Endurance
The FM25L16B devices are capable of being
accessed at least 10
14
times, reads or writes. An F-
RAM memory operates with a read and restore
mechanism. Therefore, an endurance cycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A10-A3 and column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 256 rows of
64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 20MHz clock rate.
Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop
SCK Freq
Endurance
Endurance
Years to Reach
(MHz)
Cycles/sec.
Cycles/year
Limit
12
20
37,310
1.18 x 10
85.1
11
10
18,660
5.88 x 10
170.2
11
5
9,330
2.94 x 10
340.3
Rev. 1.3
Mar. 2011
Page 8 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
