FM25L16B - 16Kb 3V SPI F-RAM
Serial Data Bus Timing
/Hold Timing
tHS
CS
tHH
SCK
tHH
tHS
HOLD
SO
tHZ
tLZ
Power Cycle Timing
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
tPU
tPD
tVR
tVF
Parameter
VDD(min) to First Access Start
Last Access Complete to VDD(min)
VDD Rise Time
Min
10
0
30
100
Max
Units
ms
µs
µs/V
µs/V
Notes
-
-
-
-
1
1
VDD Fall Time
Notes
1. Slope measured at any point on VDD waveform.
Rev. 1.3
Mar. 2011
Page 11 of 14